Electrostatic discharge (“ESD”) and electrical overstress (“EOS”) at the input/output (“I/O”) pads of an integrated circuit can result in damage to the integrated circuit (“IC”) leading to malfunction, processing errors, or even device destruction. ESD and EOS can be produced by load-inductive pulses, electromagnetic interference, or a charge imbalance between an I/O pad of an integrated circuit and an externally-grounded or pre-charged object.
Various devices and methods have been developed to protect an integrated circuit from the effects of ESD and EOS, as surveyed in “Overview of On-Chip Electrostatic Discharge Protection Design With SCR-Based Devices in CMOS Integrated Circuits” by Min-Dou Ker and Kuo-Chun Hsu, IEEE Transactions on Device and Materials Reliability, Vol. 5, No. 2, June 2005. Some approaches use silicon controlled rectifiers, or a stack of isolated, low-voltage devices, to provide a current path between a node to be protected and a power supply or ground pin. However, ESD/EOS protection for high-voltage/mixed-signal/multiple-power-domains remains difficult due to the larger power requirements of the circuits, narrow design windows, thermal limits, low leakage current requirements, and the need to avoid destructive snapback conditions. Design tradeoffs may increase fabrication cost (for example, due to the size of the devices or complexity of their fabrication) and thereby limit their application. If bidirectional ESD/EOS protection is desired, the devices may need to be duplicated for each pin, or may otherwise grow in size and complexity. Alternately, the integrated circuit devices themselves (e.g., transistors) may be modified to have some inherent ability to withstand ESD or EOS, but at a cost in power performance, larger silicon area, and higher cost.